The actual computer core is composed of the actual 65c02 CPU, an Alliance Memory AS6C4008 512k x 8 SRAM, a 32k EEPROM Atmel 28c256 and a Xilinx XC9572 CPLD.
The “computer core”, CPU, ROM, RAM and CPLD plus the VIA 65c22 and the “non-65xx-bus” native rest of the system, such as the UART 16550, V9958 and OPL2 are separated through two 74HCT245 buffers, to keep the bus lines as short as possible.
The SD card is the “killer application”, that sold the idea to us to use SPI as the main peripheral bus. The only additional hardware effort was to level shift the signals from and to the sd-card, as it runs on 3.3V while the Steckschwein uses 5V. To accomplish this, the SPI clock, SPI slave select and MOSI are converted using a 74LS07, with it’s open collector outputs pulled up to 3.3V. The other direction, MISO, is routed to one of the units of a 74HCT125, whose inputs can deal with 3.3V logic and whose outputs are TTL compliant, hence HCT.