Prototype with ATF1508 on Breadboard

We are going back to breadboarding for designing what will be the base for the new Steckschwein computer core. By “core” we mean CPU, RAM, ROM and the glue logic which will be accommodated in the ATF1508 CPLD. In order to communicate with the outside word, we also count the 16C550 UART as part of the core.

Design goals

Our main design goals are:

  • Integrate SPI into the CPLD
    Using a hardware based SPI implementation similiar to the SPI65, but tightly integrated into the CPLD will be an efficient use of the CPLD resources and will provide a much more performant SPI bus as opposed to the current semi-bit-banged solution. This way, it will be much more performant to add more SPI based components such as USB host or networking (see below).
  • Implement a priorising vectorising interrupt controller
    This will improve interrupt handling by assigning a dedicated ISR routine per interrupt source instead of one system ISR.

Other changes/optimizations

Other things that will be optimized are:

  • Simpler RESET circuit
    Our RESET circuit based on a NE555 was the same that was used on the Commodore PET machines, the VC20 and older C64s. We kept it as is for more than 10 years, through many revisions as some kind of hommage to our Commodore days. But now it is time to retire it in favor to a more state-of-the-art solution which is the Analog Devices DS1813 reset chip.
  • FT232 breakout module
    The old fashioned RS232 using the MAX232 chip will be replaced by a cheap FT232 breakout module. No need anymore for a USB to RS232 converter. We might provide both variants at some point as we are planning to replace the 16C550 UART with a 16C2752 DUART.

“Stretch goals”

Some features further down the line that we probably will implement once a performant hardware SPI bus is established and provided the CPLD’s resources allow it.

  • Replace parallel EEPROM with SPI EEPROM
    The fastest parallel Flash EEPROM has an access time of 55ns while SRAM is available with speed ratings of 12ns oder 10ns. This makes the parallel EEPROM the limiting factor for our system Speed to about 10MHz. The 65C02 and related chips are capable of at least 14MHz, even 20MHz should be possible.
    In order to get the best possible performance out of the Steckschwein, we must get rid of the parallel EEPROM.
    One way to replace it is to store the steckOS image inside an SPI Flash EEPROM and have the CPLD load it into the RAM at startup. This is heavily inspired by Andre Fachat’s MicroPET.

  • Get rid of PS/2 in favour of USB
    A USB2.0 host controller such as the Analog Devices MAX3421E could be added to provide an even more modern interface for USB keyboard/mouse and maybe even USB storage. This also means getting rid of the ATmega8 that handles PS/2 currently. Since the ATmega8 also handles Scancode to ASCII translation, that will have to be done in software.

  • Ethernet Ethernet could be added by an SPI based networking chip such as the WizNET chips.

Current status

Currently, the breadboard contains the CPU, 512k SRAM, 512k Flash EEPROM, the CPLD with the current state of the glue/banking-logic and an UART. The EEPROM contains an XMODEM upload routine. Ready to rock.

breadboard