Prototype with ATF1508 on Breadboard

We are going back to breadboarding for designing what will be the base for the new Steckschwein computer core. By “core” we mean CPU, RAM, ROM and the glue logic which will be accommodated in the ATF1508 CPLD. In order to communicate with the outside word, we also count the 16C550 UART as part of the core.

Design goals

Our main design goals are:

• Integrate SPI into the CPLD
  Using a hardware based SPI implementation similiar to the SPI65, but tighly integrated into the CPLD will be an efficient use of the CPLD resoures and will provide a much more performant SPI bus as opposed to the current semi-bit-banged solution. This way, it will be much more performant to add more SPI based components such as USB host or networking.
• Implement a priorising vectorising interrupt controller \ This will improve interrupt handling by assigning a dedicated ISR routine per interrupt source instead of one system ISR.

Other changes/optimizations

Other things that will be optimized are:

• Simpler RESET circuit
  The old Commodore-PET-derived NS555 based RESET-circuit will be replaced by an Analog Devices DS1813 reset chip
• FT232 breakout module
  The old fashioned RS232 using the MAX232 chip will be replaced by a cheap FT232 breakout module. No need anymore for a USB to RS232 converter.

“Stretch goals”

Some features further down the line that we probably will implement once a performant hardware SPI bus is established.

• Get rid of PS/2 in favour of USB
  A USB2.0 host controller such as the Analog Devices MAX3421E could be added to provide an even more modern interface for USB keyboard/mouse and maybe even USB storage. This also means getting rid of the ATmega8 that handles PS/2 currently. Since the ATmega8 also handles Scancode to ASCII translation, that will have to be done in software.

• Ethernet Ethernet could be added by an SPI based networking chip such as the WizNET chips.

Current status

Currently, the breadboard contains the CPU, 512k SRAM, 512k Flash EEPROM, the CPLD with the current state of the glue/banking-logic and an UART. The EEPROM contains an XMODEM upload routine. Ready to rock.