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Our debugging journey at VCFe began right at powering up the board the first time, when something got real hot real fast. Fair enough, and easy to spot. There was a mixup of VCC and GND at U29, a 74HCT244. Embarassing, but not that critical, as U29 is only used to connect the joystick ports to Port A of the VIA. We can live without them for now.
The mixup likely happened when I transferred the IO-board schematics from KiCad 6 to 7 while updating the symbols from the current library, which happened to be different than the old ones. I had to mirror the new symbols to fit the schematic. This meant that GND is at the top now, and VCC at the bottom. Which I happened to overlook. While routing, I was briefly wondering why U29’s bypass capacitor was at the opposite corner compared to all the other 74HCTnnn chips. I maybe should have become suspicious at that point.

Our plan for VCF2 22.0 was to assemble the first Steckschwein SBC right at our booth as some kind of show-cooking event. That only half worked, as this quickly turned into show-debugging instead of show-cooking. It was only just right before the end of VCFe 22.0, just before we had to pack everything up, we managed to get the SBC to talk to us via serial:

{{/< tweet user=“Steckschwein” id=“1653060372813733889” >/}}

Just in time for VCFe 22.0 our new SBC boards have arrived!

Be there at VCFe, when we are assembling the new Steckschwein SBC and have a few beers with us!

Save the date(s): 29.4. - 1.5.2023

ESV München OST, now at
Hermann-Weinhauser-Straße 7
81673 München

Check it out: https://vcfe.org/

Looks like the upcoming VCFe 22.0 will be a feast for the 6502-connoisseur: Andre Fachat will show his MicroPET and his 6502 multitasking operating system “GeckOS”, Armin Hierstetter will show an authentic Apple I replica, and of course we will be there, too, showing our new banking schema and our emulator.

Save the date(s): 29.4. - 1.5.2023

We really are looking forward to a glorious VCFe, which will also be back at the new old location, the sports hall of the ESV München OST, now at

This one really is a tough one to debug. At first, we suspected the VHDL code for the CPLD as the main error source, as VHDL is not our strongest suit. In fact, the decoder/banking logic is the first thing we ever really did in VHDL (apart from a few simple decoder equations the first days we were playing with GALs).

As it turned out, the VHDL was not the main problem. It sure was quite buggy and the RDY-generator had problems, but overall it was not too far off. Marko even managed to run a memory check over the entire 512k RAM, proving that even the banking logic works. Furthermore, he was able to clock the new board at 16MHz, which is another breakthrough, as a bonus.

In preparation for the build of our new CPU-Board, we purchased two WDC 65c02 in PLCC44 package from some eBay vendor. On arrival, the first interesting thing is the way they were packaged. No anti esd packaging, only a plastic bag, which we found sketchy enough to post on Twitter.

Next, WDC reacted to that tweet, stating that these might be not genuine or be at least very old.

{{/< tweet user=“steckschwein” id=“1532446031127904256” >/}}