Breadboard

We are going back to breadboarding for designing what will be the base for the new Steckschwein computer core. By “core” we mean CPU, RAM, ROM and the glue logic which will be accommodated in the ATF1508 CPLD. In order to communicate with the outside word, we also count the 16C550 UART as part of the core.

Design goals

Our main design goals are:

• Integrate SPI into the CPLD
  Using a hardware based SPI implementation similiar to the SPI65, but tighly integrated into the CPLD will be an efficient use of the CPLD resoures and will provide a much more performant SPI bus as opposed to the current semi-bit-banged solution. This way, it will be much more performant to add more SPI based components such as USB host or networking.
• Implement a priorising vectorising interrupt controller \ This will improve interrupt handling by assigning a dedicated ISR routine per interrupt source instead of one system ISR.

Other changes/optimizations

Other things that will be optimized are: