Cpld

We are going back to breadboarding for designing what will be the base for the new Steckschwein computer core. By “core” we mean CPU, RAM, ROM and the glue logic which will be accommodated in the ATF1508 CPLD. In order to communicate with the outside word, we also count the 16C550 UART as part of the core.

Design goals

Our main design goals are:

• Integrate SPI into the CPLD -> DONE
  Using a hardware based SPI implementation similiar to Daryl Rictor’s SPI65, but tightly integrated into the CPLD will be an efficient use of the CPLD resources and will provide a much more performant SPI bus as opposed to the current semi-bit-banged solution. This way, it will be much more performant to add more SPI based components such as USB host or networking (see below).
  Update: Done! We decided to use Andre Fachat’s SPI implementation from his MicroPET. The main advantage over rolling our own is - it’s already there. Another main advantage over other existing Implementation is that the MicroPET one is pretty small, which is important when CPLD resources are at a premium.
• Implement a priorising vectorising interrupt controller
  This will improve interrupt handling by assigning a dedicated ISR routine per interrupt source instead of one system ISR.
  Update: We are already scratching the limit of the ATF1508. The PLCC84 version we use in our prototype can not handle more pins, so we are unable to add the inputs needed for all the interrupt sources we need. While this is unfortunate, we have not scrapped the idea of an interrupt controller. We might move to the TQFP-100 version at some point, which obviously has more pins.
• DUART instead of UART
  Replacing our trusty 16C550 with a 16C2752 DUART will provide two serial interfaces without increasing the chip count.
  With two serial ports, we will be able to upload programs on one serial port, while observing the output on the other one. Also, a separate upload interface will allow us to explore UART interrupts on the other.

Other changes/optimizations

Other things that will be optimized are:

Since we introduced our new banking logic to access 512k RAM, our glue logic is being accommodated by a Xilinx XC9572 (without XL) CPLD. This component has long been deprecated when we started using it. We chose it because it was what we had available. The upgrade path would be the successor family XC95..XL. Those have been rather expensive lately, and finally AMD/Xilinx axed their whole CPLD line in 2024, leaving us at a dead end. Where do we go from here? The market for CPLDs is not exactly growing. Only a few manufacturers are still actively producing them.

This one really is a tough one to debug. At first, we suspected the VHDL code for the CPLD as the main error source, as VHDL is not our strongest suit. In fact, the decoder/banking logic is the first thing we ever really did in VHDL (apart from a few simple decoder equations the first days we were playing with GALs).

As it turned out, the VHDL was not the main problem. It sure was quite buggy and the RDY-generator had problems, but overall it was not too far off. Marko even managed to run a memory check over the entire 512k RAM, proving that even the banking logic works. Furthermore, he was able to clock the new board at 16MHz, which is another breakthrough, as a bonus.

In preparation for the build of our new CPU-Board, we purchased two WDC 65c02 in PLCC44 package from some eBay vendor. On arrival, the first interesting thing is the way they were packaged. No anti esd packaging, only a plastic bag, which we found sketchy enough to post on Twitter.

Next, WDC reacted to that tweet, stating that these might be not genuine or be at least very old.

{{/< tweet user=“steckschwein” id=“1532446031127904256” >/}}

The biggest limitation of any 8 bit CPU such as our beloved 65C02 is the amount of memory that the CPU can address. With 16 address lines, the addressable memory is maxed out at 64k. All ROM and RAM has to be crammed into there. With the 6502 being a memory mapped architecture, IO devices need their addresses there, too.

In order to expand the amount of usable memory, some trickery is necessary. For example, the developers of the C64 came up with a rather clever hack to cram 20k of ROM and full 64k of RAM and IO area into 64k address space by introducing a register that enables the programmer to switch off the ROM, giving access to the underlying RAM. When the ROM is enabled, writes to the addresses go into the RAM below. We decided to mimic this behaviour in our current implementation of the Steckschwein glue logic.

In der letzten Zeit war es hier etwas still ums Steckschwein, was aber nicht als Indiz für Untätigkeit gelten soll. Hauptsächlich haben wir uns auf das Schreiben von Code konzentriert, die Shell wurde weiterentwickelt, etc. Darüberhinaus gab es erste Experimente mit CPLDs. Auf dieser Basis sollen ja zukünftige Verbesserungen der Hardware entstehen, begonnen bei einem eigenständigen SPI-Controller bis hin zur Zusammenfassung der bestehenden Glue-Logik rund um die Adressdekodierung. Da ich mir zu diesem Zweck testhalber solche CPLD-Entwicklungsplatinchen auf Basis des XilinX XC9572XL habe kommen lassen, stellte sich also als erstes die Frage, wie sich dessen 3.3V-basierte Logik mit dem 5V-Steckschwein vertragen würde. Zum CPLD hin wären ja keine Probleme zu erwarten, denn die IO-Pins des XC9572XL sind 5V-tolerant. Die Richtung vom CPLD zum Steckschwein bedarf also besonderer Betrachtung, denn es muss sichergestellt werden, dass alle Bausteine am Bus, die mit dem CPLD verbunden sind, dessen 3.3V-Logikpegel zuverlässig erkennen. Als einzige wirklich problematische Komponente stellte sich hier - wieder mal - der auf meinem Steckschwein eingesetzte (Marko nutzt einen 65c02 von Rockwell) WDC 65c02 heraus. Das Datenblatt gibt als “Input High Voltage”, also die Spannung, ab der auf der entsprechenden Leitung (BE, D0 -D7, RDY, /SO, /IRQ, /NMI, PHI2, /RES) eine logische 1 erkannt wird, mit “VDD*0.7” an. Bei einer Betriebsspannung von 5V also 3,5V. Mit 3.3V-Pegeln also schonmal nicht kompatibel. Geschweige denn mit TTL-Pegeln. Die leider so ziemlich alle auf dem Datenbus liegenden Bausteine verwenden, mit Ausnahme der WDC 65c22 VIA.  Alle anderen Bausteine geben im Datenblatt als “High Level Output Voltage” Werte von 2.4-2.7V an.  Kann also gar nicht passen. Dass das Steckschwein trotzdem mit dem WDC funktioniert ist ganz offenbar Glück bzw. der Tatsache geschuldet, dass der Chip dann doch toleranter ist als das Datenblatt uns glauben machen will.  Trotzdem nicht sauber. In zukünftigen Revisionen müssen wir also zwischen CPU und Datenbus einen 74HCT245-Buffer eindesignen, der durch TTL-kompatible Eingänge und CMOS-Ausgänge die Pegelunterschiede ausbügelt. Gleiches gilt auch für weitere Experimente mit dem 3.3V-CPLD. Oder auch mit dessen 5V-Vorgänger XC9572.  Zusammenfassend also noch einmal die Besonderheiten des 65c02 von WDC: