Memory

The 28C256 EEPROM, which holds the BIOS, has been our go-to choice since the early breadboard days. Before that, we relied on EPROMs, which required UV erasure before every upgrade—a time-consuming and inconvenient process. Switching to an EEPROM significantly improved our workflow, reducing turnaround time.

However, the 28C256 has a couple of drawbacks:

• It cannot be written in-circuit since it requires a 12V programming voltage, which the Steckschwein does not provide.
• It is slow, with an access time of 150ns, forcing us to introduce wait states to slow down the CPU when accessing the BIOS.

Because of these limitations, using ROM routines isn’t ideal from a performance standpoint. As a result, the BIOS’s sole function is to load the steckOS bootloader from an SD card into RAM and start it.

Some time ago we introduced a tiny tool called ppmview.prg in our collection of tools and progs for our Steckschwein. The ppmview.prg, as the name already tells, is able to load an image in ppm (Portable BitMap) format with a maximum size of 256x212px and displays it on the screen.

The first version of ppmview was released in 2018 and since then we just use the SCREEN 8 (MSX) also known as graphic mode 7 (RGB).
Mode 7 is a bitmap mode where we have 256 colors available and each pixel requires 1 Byte for their color information. The 1 Byte color information must be stored in VRAM encoded as GRB 3:3:2 (green, red, blue), which means 3 Bit green, 3 Bit red and 2 Bit blue.
On the other side we have the PPM color information - which is 24Bit RGB - so we have to adapt or map the 24Bit to our 8 Bit GRB color value in some way.
It becomes apparent that this comes with a price, namely the loss of color information. Especially the blue part of the pixel is just 2 Bit, hence we have 4 levels of blue per pixel available only. The following screenshot from our Emulator shows the loss of color information.

Our debugging journey at VCFe began right at powering up the board the first time, when something got real hot real fast. Fair enough, and easy to spot. There was a mixup of VCC and GND at U29, a 74HCT244. Embarassing, but not that critical, as U29 is only used to connect the joystick ports to Port A of the VIA. We can live without them for now.
The mixup likely happened when I transferred the IO-board schematics from KiCad 6 to 7 while updating the symbols from the current library, which happened to be different than the old ones. I had to mirror the new symbols to fit the schematic. This meant that GND is at the top now, and VCC at the bottom. Which I happened to overlook. While routing, I was briefly wondering why U29’s bypass capacitor was at the opposite corner compared to all the other 74HCTnnn chips. I maybe should have become suspicious at that point.

Our plan for VCF2 22.0 was to assemble the first Steckschwein SBC right at our booth as some kind of show-cooking event. That only half worked, as this quickly turned into show-debugging instead of show-cooking. It was only just right before the end of VCFe 22.0, just before we had to pack everything up, we managed to get the SBC to talk to us via serial:

{{/< tweet user=“Steckschwein” id=“1653060372813733889” >/}}

Just in time for VCFe 22.0 our new SBC boards have arrived!

Be there at VCFe, when we are assembling the new Steckschwein SBC and have a few beers with us!

Save the date(s): 29.4. - 1.5.2023

ESV München OST, now at
Hermann-Weinhauser-Straße 7
81673 München

Check it out: https://vcfe.org/

This one really is a tough one to debug. At first, we suspected the VHDL code for the CPLD as the main error source, as VHDL is not our strongest suit. In fact, the decoder/banking logic is the first thing we ever really did in VHDL (apart from a few simple decoder equations the first days we were playing with GALs).

As it turned out, the VHDL was not the main problem. It sure was quite buggy and the RDY-generator had problems, but overall it was not too far off. Marko even managed to run a memory check over the entire 512k RAM, proving that even the banking logic works. Furthermore, he was able to clock the new board at 16MHz, which is another breakthrough, as a bonus.