Microchip

We are going back to breadboarding for designing what will be the base for the new Steckschwein computer core. By “core” we mean CPU, RAM, ROM and the glue logic which will be accommodated in the ATF1508 CPLD. In order to communicate with the outside word, we also count the 16C550 UART as part of the core.

Design goals

Our main design goals are:

• Integrate SPI into the CPLD -> DONE
  Using a hardware based SPI implementation similiar to Daryl Rictor’s SPI65, but tightly integrated into the CPLD will be an efficient use of the CPLD resources and will provide a much more performant SPI bus as opposed to the current semi-bit-banged solution. This way, it will be much more performant to add more SPI based components such as USB host or networking (see below).
  Update: Done! We decided to use Andre Fachat’s SPI implementation from his MicroPET. The main advantage over rolling our own is - it’s already there. Another main advantage over other existing Implementation is that the MicroPET one is pretty small, which is important when CPLD resources are at a premium.
• Implement a priorising vectorising interrupt controller
  This will improve interrupt handling by assigning a dedicated ISR routine per interrupt source instead of one system ISR.

Other changes/optimizations

Other things that will be optimized are:

Since we introduced our new banking logic to access 512k RAM, our glue logic is being accommodated by a Xilinx XC9572 (without XL) CPLD. This component has long been deprecated when we started using it. We chose it because it was what we had available. The upgrade path would be the successor family XC95..XL. Those have been rather expensive lately, and finally AMD/Xilinx axed their whole CPLD line in 2024, leaving us at a dead end. Where do we go from here? The market for CPLDs is not exactly growing. Only a few manufacturers are still actively producing them.